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1 ? fn6372.2 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2006, 2007. all rights reserved all other trademarks mentioned are the property of their respective owners. isl59311 differential video amplifier with common mode sync encoder and serial digital interface the isl59311 is a high bandwidth triple differential amplifier with integrated encoding of video sync signals. the inputs are suitable for handling high speed video or other communications signals in either single-ended or differential form, and the common-mode input range extends all the way to the negative rail enabling ground-referenced signaling in single supply applications. the high bandwidth enables differential signaling onto standard twisted-pair or coax with very low harmonic distortion, while internal feedback ensures balanced gain and phase at the outputs reducing radiated emi and harmonics. embedded logic encodes standard video horizontal and vertical sync signals onto the common mode of the twisted pair(s), transmitting this additional information without the requirement for additional buffers or transmission lines. the isl59311 enables significant system cost savings when compared with discrete line driver alternatives. the digital block of the chip is a data transceiver which is intended to drive one twisted pair line. the maximum baudrate for this block is 50mbps. the isl59311 is available in a 32 ld qfn package and is specified for operation over th e -40c to +85c temperature range. applications ? twisted-pair drivers ? differential line drivers ? vga over twisted-pair ? transmission of analog signals in a noisy environment features ? fully differential inputs, outputs, and feedback ? 650mhz -3db bandwidth ? 1500v/s slew rate ? -70db distortion at 20mhz ? single 5v operation ? 50ma minimum output current ? low power: 57ma total supply current ? pb-free plus anneal available (rohs compliant) block diagram ordering information part number (note) part marking tape & reel package (pb-free) pkg. dwg. # isl59311irz 59311 irz - 32 ld qfn l32.5x6a ISL59311IRZ-T13 59311 irz 13? 32 ld qfn l32.5x6a note: intersil pb-free plus anneal products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. v in a+ v out c+ cm a cm b cm c hsync vsync disable sync to common mode translation + - + - + - txdata gnd d v ccd rxdata transmit s out + s out - s in - s in + s data v out c- v out b+ v out b- v out a+ v out a- gnd a v cca v in a- v in b+ v in b- v in c+ v in c- v ccs + - v ccs domain v ccd domain v cca domain data sheet april 4, 2007
2 fn6372.2 april 4, 2007 pinout isl59311 (32 ld qfn) thermal pad 25 24 23 22 21 20 19 32 31 30 29 28 10 11 12 13 14 1 2 3 4 5 6 7 vsync hsync v in b+ v in b- v in c+ v in c- gnd a v out c- v out b+ v out b- v out c+ gnd a gnd d v ccd v in a- vi in a+ disable v out a+ v out a- gnd d s data transmit s out - nc 8 9 18 17 15 27 16 26 nc s out + s in - s in + v ccs v ccs v cca gnd a pin descriptions pin name descriptions equivalent circuit v in a, v in b, v in c differential video inputs v out a, v out b, v out c differential video outputs to transmission line hsync, vsync horizontal and vertical sync inputs to be encoded disable disable video amplifiers signal. logic low enables the video amplifiers. logic high disables the video amplifiers, reducing v cca power consumption. the serial digital interface is always enabled regardless of the state of the disable pin. transmit transmit/receive logic input. logic high: transmits data from the s data pin data down the transmission line. logic low: data received from the transmission line is output on the s data pin. s out differential serial data outputs to transmission line s in differential serial data i nputs from transmission line h,v gnda gnda env tr gnda isl59311
3 fn6372.2 april 4, 2007 s data digital data input/output. when transmit is high, this is an i nput, receiving the serial data to be transmitted over the s out pins. when transmit is low, this is an ou tput, representing the data received on the s in pins. v ccs power supply for s data i/o pin - sets input thresholds and output swing. typically set to 3.3v or 5v. v ccd v cc for line interface section (5v) gnd d digital ground for the serial digital interface v cca v cc for the video amplifiers (5v) gnd a analog ground for the video amplifiers nc no connection. do not connect these pins to anything. leave these pins floating! pin descriptions (continued) pin name descriptions equivalent circuit txrx diff data isl59311
4 fn6372.2 april 4, 2007 absolute maxi mum ratings (t a = +25c) supply voltage (v cca , v ccd ) . . . . . . . . . . . . . . . . . . . . . . . . . +6.5v maximum output continuous current . . . . . . . . . . . . . . . . . . 70ma storage temperature range . . . . . . . . . . . . . . . . . .-65c to +150c operating junction temperature . . . . . . . . . . . . . . . . . . . . . . +125c ambient operating temperature . . . . . . . . . . . . . . . .-40c to +85c input/output voltages all signal (non-supply) pins . . . . . . . . . . . . -0.6v to v cca + 0.6v esd classification human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3000v machine model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250v caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. note: all parameters having min/max specific ations are guaranteed. typical values are for information purposes only. unless othe rwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a electrical specifications v cca = v ccd = v ccs = +5v, gnd a = gnd d = 0v, t a = +25c, v in = 0v, r l = 200 , unless otherwise specified. description condition min typ max unit video amplifier electrical characteristics output voltage range 1v cc -1 v output impedance, disabled 10 m ac performance bandwidth, -3db a v = 2, v out = 200mv 650 mhz v out = 2v 600 mhz differential slew rate, v out = 2v p-p 1500 v/s settling time (0.1%, 2v p-p ) 20 ns gain bandwidth product 1300 mhz 2nd harmonic distortion 20mhz, r l = 200 -70 dbc 3rd harmonic distortion 20mhz, r l = 200 -70 dbc hostile crosstalk 75 db differential phase @100mhz 0.01 differential gain @100mhz 0.01 % input characteristics input referred offset voltage -10 1 10 mv input bias current 2612a differential input impedance 10 m differential input range 0.75 v common mode input voltage range -0.3 v cca -2.6 v input referred noise 15 nv/ hz cmrr v cm = 0v to 2v 60 75 db output characteristics output peak current 40 60 ma output voltage range 1v cc -1 v dc performance voltage gain 1.90 1.95 2.00 v/v psrr rejection of v cca 60 75 db isl59311
5 fn6372.2 april 4, 2007 digital transceiver block electrical characteristics transmitter dc characterstics s out differential output voltage no load v ccd v r l = 100 (figure 1a) 3.0 3.3 v change in magnitude of driver differential s out for complementary output states r l = 100 (figure 1a) |(s out +) - (s out -)| .08 0.2 v s out common-mode voltage (deviation from v ccd /2) r l = 100 (figure 1a) -0.1 0.06 +0.1 v s out short circuit current driving high, output tied to gnd 95 110 ma driving low, output tied to v ccd 95 110 ma s out leakage current s out (transmit = gnd) 2 100 na transmitter switching characteristics maximum data rate r l = 100 , (figure 1a) 50 mbps differential propagation delay t plh (figure 2, r diff = 100 ) 6 10 ns t phl (figure 2, r diff = 100 ) 6 10 ns differential output skew |t plh ? t phl | (figure 2, r diff = 100 )24ns output enable time t pzh : driver enable to output high (figure 3, i sink = 1ma, i source = off) 420ns t pzl : driver enable to output low (figure 3, i sink = off, i source = 1ma) 620ns output disable time t phz : output high to output disabled (figure 3, i sink = 25ma, i source = off) 28 35 ns t plz : output low to output disabled (figure 3, i sink = off, i source = 25ma) 28 35 ns disabled output leakage 2 100 na receiver dc characteristics s in input hysteresis v cm = 2.5v 2 30 50 mv s in input range gnd - 0.5 v cc +0.5 v s in input resistance; each input to gnd 2.5 3.0 3.5 k receiver switching characteristics maximum data rate driven with 100mv differential signal (figure 4, note 4) 50 mbps receiver input to output propagation delay t plh (figure 4) 4.7 8 ns t phl (figure 4) 5.5 8 ns receiver skew |t plh ? t phl | (figure 4) 0.8 2 ns t rise /t fall 100k ii10pf load 2 ns receiver enable to output high 15 20 ns receiver enable to output low 35 42 ns receiver high to hi-z 15 25 ns receiver low to hi-z 10 20 ns electrical specifications v cca = v ccd = v ccs = +5v, gnd a = gnd d = 0v, t a = +25c, v in = 0v, r l = 200 , unless otherwise specified. (continued) description condition min typ max unit isl59311
6 fn6372.2 april 4, 2007 notes: 1. all currents into device pins are positive; all currents out of device pins are negative. all vo ltages are referenced to devi ce ground unless otherwise specified. 2. v ccs current is equal to the v ccs voltage applied divided by the v ccs input impedance. some additional current is consumed when s data is driving high into the external load. 3. applies to peak current. see ?typical pe rformance curves? for more information. 4. guaranteed by characterization but not tested. system logic inputs dc characteristics vsync, hsync, transmit, and disable input characteristics input high voltage v ih 2v input low voltage v il 0.8 v vsync, hsync, transmit input current i in 1 5 a disable pin pull-down resistance to gnda r disable 500 k s data input characteristics (transmit = v ccd ) input high voltage v ih 0.7 v ccs v input low voltage v il 0.3 v ccs v input current i in 0.001 1 a s data output characteristics (transmit = gnd) high output level sourcing 4ma to gnd 4.5 4.7 v low output level sinking 4ma from v ccs 0.3 0.4 v short circuit output current driving high, output tied to gnd 20 ma driving low, output tied to v ccs 40 ma power supply characteristics v cca operating range 4.5 5.5 v v cca supply current (all 3 channels) operating (disable = gnd) 50 60 ma disabled (disable = v cca )2.33ma v ccd operating range 4.5 5.5 v v ccd supply current 712ma v ccs input impedance v ccs = 5v (note 2) 4 5 6 k electrical specifications v cca = v ccd = v ccs = +5v, gnd a = gnd d = 0v, t a = +25c, v in = 0v, r l = 200 , unless otherwise specified. (continued) description condition min typ max unit isl59311
7 fn6372.2 april 4, 2007 test circuits and waveforms figure 1a. v od and v oc figure 1b. v od with common mode load figure 1. dc driver test circuits figure 2a. test circuit figure 2b. measurement points figure 2. driver propagation delay and differential transition times figure 3a. test circuit figure 3b. measurement points figure 3. driver data rate figure 4a. test circuit figure 4b. measurement points figure 4. receiver propagation delay and data rate d s data v od v oc 50 50 s out - s out + d s data v od 50 50 s out - s out + v cm 0v to 5v d s data signal generator c l = 50pf 100 s out - s out + c l = 50pf s out - 5v 0v 2.5v 2.5v v oh v ol s out + t plh t phl diff out t r +v od -v od 90% 90% t f 10% 10% di skew = |t plh - t phl | ( s out + - s out -) d s data signal generator s out i sink i source 50pf s out s out t plz transmit 10% t pzl 1.5v t phz t pzh 90% 3.5v 2.5v 2.5v signal generator r s data s in + s in - 2.5v 50pf s data 4.0v 1.0v t plh 2.5v 2.5v v ccs = 5v 0v 1.5v 1.5v t phl s in + isl59311
8 fn6372.2 april 4, 2007 typical performance curves figure 5. common mode output figure 6. differential frequency response for various r l - diff (channel a) figure 7. differential frequency response for various r l - diff (channel b) figure 8. differential frequency response for various r l - diff (channel c) figure 9. differential frequency response for various c l - diff (channel a) figure 10. differential frequency response for various c l - diff (channel b) time (0.5ms/div) blue cm out (ch c) green cm out (ch b) red cm out (ch a) v sync h sync voltage (0.5v/div) voltage (2.5v/div) v cca = 5v c l = 0pf chan a r l = 500 r l = 200 r l = 100 r l = 50 v cca = 5v c l = 0pf chan b r l = 500 r l = 200 r l = 100 r l = 50 v cca = 5v c l = 0pf chan c r l = 500 r l = 200 r l = 100 r l = 50 v cca = 5v r l = 200 chan a c l = 12pf c l = 8.2pf c l = 4.7pf c l = 2.2pf v cca = 5v r l = 200 chan b c l = 12pf c l = 8.2pf c l = 4.7pf c l = 2.2pf isl59311
9 fn6372.2 april 4, 2007 figure 11. differential frequency response for various c l - diff (channel c) figure 12. total harmonic distortion figure 13. 2 nd harmonic distortion figure 14. 3 rd harmonic distortion figure 15. differential large signal transient response figure 16. differential small signal transient response typical performance curves (continued) v cca = 5v r l = 200 chan c c l = 12pf c l = 8.2pf c l = 4.7pf c l = 2.2pf v cca = 5v r l = 200 thd output c output b output a v cca = 5v r l = 200 2 nd harmonic output b output a output c v cca = 5v r l = 200 3 rd harmonic output c output b output a r l = 200 diff c l = 0pf time (20ns/div) voltage (235mv/div) fall t = 1.1ns rise t = 1.2ns time (20ns/div) voltage (120mv/div) rise t = 1.4ns fall t = 1.3ns r l = 200 diff c l = 0pf isl59311
10 fn6372.2 april 4, 2007 operational descripti on and application information introduction the isl59311 is designed to differentially drive composite rgb video signals onto twisted pair lines, while simultaneously encoding horizontal and vertical sync signals as common mode output. the entire video signal plus sync can therefore be transmitted on 3 twisted pairs of wire. when utilizing cat-5 cable, the 4th available twisted pair can be used for transmission of audio, data or control information. the distribution of composite video over standard cat-5 cable enables enormous cost and labor savings compared with traditional coaxial cable, when considering both the relative low price and ease of pulling cat-5 cable. the digital block of the chip is a data transceiver which is intended to drive one twisted pair line. the maximum baudrate for this block is 50mbps. functional description the isl59311 provides three fully differential high-speed amplifiers, suitable for driving high-resolution composite video signals onto twisted pair or standard coaxial cable. the input common-mode range ex tends to the negative rail, allowing simple ground-referenced input termination to be used with a single supply. the amplifiers provide a fixed gain of +2 to compensate for standard video cable termination schemes. horizontal and vertical sync signals (h sync and v sync ) are passed to an internal logic encoding block to encode the sync information as three discrete signals of different voltage levels. generally, in differential amplifiers an external v ref pin is used to control the common mode level of the differential output; in the case of the isl59311 the v ref of each of the three internal amplifier channels receives a signal from the logic encoding block with encoded h sync and v sync information. the final output consists of three fully differential video signals, with sync encoded on the common mode of each of the three rgb differential signals. h sync and v sync can easily be separated from the differenti al output signals, decoded and transmitted along with the rgb video signals to the video monitor. sync transmission the isl59311 encodes h sync and v sync signals on the common mode output of the differential video signals; red, green and blue respectively. data sheet table 1 shows the common mode levels for the different sync input combinations. note that the sum of the common mode voltages results in a fixed average dc level with no ac content. this dramatically reduces emi radiation into any common mode signal along the twisted pairs of cat 5 cable. extract common mode sync and decode h sync and v sync h sync and v sync can be regenerated from the common mode sync output voltages. the relationships between h sync , v sync and the 3 common mode levels are given by table 1. the common mode levels are easily separated from the differential outputs of t he isl59311 using this simple resistor network at the cable receiver input of each differential channel; see figure 20. figure 17. package power dissipation vs ambient temperature figure 18. package power dissipation vs ambient temperature typical performance curves (continued) jedec jesd51-7 high effective thermal conductivity test board - qfn exposed diepad soldered to pcb per jesd51-5 3 2.5 2 1.5 1 0.5 0 0 255075100 150 ambient temperature (c) power dissipation (w) 2.857w j a = 3 5 c / w q f n 3 2 125 85 jedec jesd51-3 and semi g42-88 (single layer) test board 0.8 0.7 0.5 0.3 0.2 0.1 0 0 255075100 150 ambient temperature (c) power dissipation (w) 125 85 0.6 0.4 j a = 1 2 5 c / w q f n 3 2 758mw table 1. sync signal encoding hsync vsync common mode a (red) common mode b (green) common mode c (blue) low high 3.0 2.0 2.5 low low 2.5 3.0 2.0 high low 2.0 3.0 2.5 high high 2.5 2.0 3.0 isl59311
11 fn6372.2 april 4, 2007 twisted pair termination the schematic in figure 20 illustrates a termination scheme for 50 series termination and a 100 twisted pair cable. note rcm is the common mode termination to allow measurement of v cm and should not be too small since it loads the isl59311; a little over a 100 is recommended for rcm. video transmission the isl59311 is a twisted pair differential line driver directed at the transmission of video signals through cables up to 100 feet; however, as signal losses increase with transmission line length the isl59311 will need additional support to equalize video signals along longer twisted pair transmission lines. a full solution to accomplish this is the sxga video transmission system presented in the isl59311 data sheet. note the inclusion of the el9111 for signal equalization of up to 1000ft of cat-5 cable and common mode extraction; see data sheet for additional information on the el9111. long distance video transmission the sxga video transmission system makes it possible to transmit red, green and blue (rgb) video plus sync up to 1000ft through cat-5 cable. the input to the sxga video transmission system is the output of a video source transmitting rgb video signals plus sync. the signals are received initially by the isl59311; which converts the single ended input rgb signals to three fully differential waveforms with sync encoded on the discr ete common modes of each color channel and then drives the signals through a length of cat-5 cable. the signal is received by the el9111, which can provide 6-pole equalization for both high and low frequency signal transmission line losses. then the el9111 converts the differential rgb video signals back into single ended format while extracting the common mode component for decoding. the single ended rgb signal is taken directly from the output of the el9111 and is ready for the output device. the el9111 common mode decoder circuit receives the common mode signals and decodes them and transmits h sync and v sync to the output device. disabling the amplifiers with the disable pin the disable pin must be a logic low for normal operation of the video amplifiers. when disable is taken high, the amplifiers are disabled, reducing supply v cca supply current. (the disable pin has no effect on the serial digital transceiver - it is always enabled as long as power is applied to v ccd .) serial digital transceiver operation the digital transceiver is a half-duplex design, either receiving data on the s in pins and sending it out on the s data pin, or transmitting data from the s data pin out on some the 2 s out pins. the digital transceiver operates in a high speed (up to 50mbaud) differential mode. the s data pin is the half-duplex logic-le vel transmit and receive data pin. s data is an output when transmit = low (receive mode) and an input when transmit = high (transmit mode). this can be made to work with existing designs that use independent transmit and receive pins by connecting s data directly to the transmit pin and through a resistor to the receive pin. figure 21 shows an example of how to interface the isl59311 with an rs485 transceiver. v ccd is the power source for the digital line interface drivers and receivers. - + - + - + v in av out a disable v ref - + - + - + v in bv out b disable v ref - + - + - + v in cv out c disable v ref logic decoding cm a cm b cm c v sync h sync disable disable figure 19. video driver block diagram - + v ref - + twisted pair z o =100 50 50 50 50 120 v cm (rcm: should be >100 ) (for loading considerations) figure 20. twisted pair termination isl59311
12 fn6372.2 april 4, 2007 digital transceiver block diagram proper layout technique a critical concern with any pcb layout is the establishment of a ?healthy? ground plane. it is imperative to provide ground planes terminated close to inputs to minimize input capacitance. additionally, the ground plane can be selectively removed from inputs to prevent load and supply currents from flowing near the input nodes. in general the following guidelines apply to all pcb layout: ? keep all traces as short as possible. ? keep power supply bypass components as close to the chip as possible - extremely close. ? create a healthy ground with low impedance and continuous ground pathways available to all grounded components board-wide. ? in high frequency applications on multi-level boards try to keep one level of board with continuous ground plane and minimum via cutouts - providing it is affordable. ? provide extremely short loops from power pin to ground. ? if it is affordable, a ferrite bead is always of benefit to isolate device from power suppl y noise and the rest of the circuit from the noise of the device. 0.1 f + d r 17 13 19 11 12 7 v ccs gnd s data transmit s out - s out + +5v 0.1 f + d r 6 7 8 1 2 3 4 5 v cc gnd ro re de di a/y b/z +5v r t r t isl83088 isl59311 15 16 s in - s in + figure 21. rs-485 serial interface connection diagram r1 encoding r3 txdata txen rdata transmit s out + s out - s in - s in + (s data ) (s data ) twisted pair line isl59311
13 fn6372.2 april 4, 2007 power dissipation calculation when switching at high speeds, or driving heavy loads, the isl59311 drive capability is ultima tely limited by the rise in die temperature brought about by inte rnal power dissipation. for reliable operation die temperature must be kept below t jmax (+125c). it is necessary to calc ulate the power dissipation for a given application prior to selecting package type. power dissipation may be calculated: where: ?v s is the total power supply to the isl59311 (= v ccd ) ?v out is the swing on the output (v h - v l ) ?c l is the load capacitance ?c int is the internal load capacitance (80pf max) ?i s is the quiescent supply current ? f is frequency having obtained the application's power dissipation, the maximum junction temperature can be calculated: where: ?t jmax is the maximum junction temperature (+125c) ?t max is the maximum ambient operating temperature ? pd is the power dissipation calculated above ja is the thermal resistance, j unction to ambient, of the application (package + pcb combination). refer to the package power dissipation curves. pd v s i s () 4 1 c int v s 2 f () c l v out 2 f () + = t jmax t max ja pd + = isl59311
14 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6372.2 april 4, 2007 isl59311 quad flat no-lead plastic package (qfn) micro lead frame pl astic package (mlfp) pin #1 i.d. mark 2 1 3 (n-2) (n-1) n (n/2) 2x 0.075 top view (n/2) ne 2 3 1 pin #1 i.d. (n-2) (n-1) n b l n leads bottom view detail x plane seating n leads c see detail "x" a1 (l) n leads & exposed pad 0.10 side view 0.10 b a m c c b a e 2x 0.075 c d 3 5 7 (e2) (d2) e 0.08 c c (c) a 2 c l32.5x6a (one of 10 packages in mdp0046) 32 lead quad flat no-lead plastic package (compliant to jedec mo-220) symbol millimeters notes min nominal max a 0.80 0.90 1.00 - a1 0.00 0.02 0.05 - d 5.00 bsc - d2 2.48 ref - e 6.00 bsc - e2 3.40 ref - l 0.45 0.50 0.55 - b 0.20 0.22 0.24 - c 0.20 ref - e 0.50 bsc - n 32 ref 4 nd 7 ref 6 ne 9 ref 5 rev 0 9/05 notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. tiebar view shown is a non-functional feature. 3. bottom-side pin #1 i.d. is a diepad chamfer as shown. 4. n is the total number of terminals on the device. 5. ne is the number of terminals on the ?e? side of the package (or y-direction). 6. nd is the number of terminals on the ?d? side of the package (or x-direction). nd = (n/2)-ne. 7. inward end of terminal may be s quare or circular in shape with radius (b/2) as shown.

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